In testing high density and high speed electrical devices such as LSI and VLSI circuits, high performance probe contactors or test contactors must be used. The electronic packaging and interconnection of a contact structure of the present invention is not limited to the application of testing and burn-in of semiconductor wafers and die, but is inclusive of testing and burn-in of packaged semiconductor devices, printed circuit boards and the like. However, for the convenience of explanation, the present invention is described mainly with reference to a probe card to be used in semiconductor wafer testing.
In the case where semiconductor devices to be tested are in the form of a semiconductor wafer, a semiconductor test system such as an IC tester is usually connected to a substrate handler, such as an automatic wafer prober, to automatically test the semiconductor wafer. Such an example is shown in FIG. 1 in which a semiconductor test system has a test head 100 which is ordinarily in a separate housing and electrically connected to the test system with a bundle of cables. The test head 100 and the substrate handler 400 are mechanically connected with one another by means of a manipulator 500 and a drive motor 510 shown FIG. 1. The semiconductor wafers to be tested are automatically provided to a test position of the test head by the substrate handler.
On the test head, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from the semiconductor wafer under test are transmitted to the semiconductor test system wherein they are compared with expected data to determine whether IC circuits on the semiconductor wafer function correctly.
The test head and the substrate handler are connected with an interface component 140 consisting of a performance board 120 which is a printed circuit board having electric circuit connections unique to a test head's electrical footprint, coaxial cables, pogo-pins and connectors. The test head 100 includes a large number of printed circuit boards 150 which correspond to the number of test channels. Each of the printed circuit boards has a connector 160 to receive a corresponding contact terminal 121 of the performance board 120. A "frog" ring 130 is mounted on the performance board 120 to accurately determine the contact position relative to the substrate handler 400. The frog ring 130 has a large number of contact pins 141, such as ZIF connectors or pogo-pins, connected to contact terminals 121, through coaxial cables 124.
FIG. 2 shows, in more detail, a structure of the substrate handler 400, the test head 100 and the interface component 140 when testing a semiconductor wafer. As shown in FIG. 2, the test head 100 is placed over the substrate handler 400 and mechanically and electrically connected to the substrate handler through the interface component 140. In the substrate handler 400, a semiconductor wafer 300 to be tested is mounted on a chuck 180. A probe card 170 is provided above the semiconductor wafer 300 to be tested. The probe card 170 has a large number of probe contactors (such as cantilevers or needles) 190 to contact with circuit terminals or contact targets in the IC circuit of the wafer 300 under test.
Electrical terminals or contact receptacles of the probe card 170 are electrically connected to the contact pins 141 provided on the frog ring 130. The contact pins 141 are also connected to the contact terminals 121 of the performance board 120 with coaxial cables 124 where each contact terminal 121 is connected to the printed circuit board 150 of the test head 100. Further, the printed circuit boards 150 are connected to the semiconductor test system through the cable 110 having several hundreds of inner cables.
Under this arrangement, the probe contactors 190 contact the surface of the semiconductor wafer 300 on the chuck 180 to apply test signals to the semiconductor wafer 300 and receive the resultant output signals from the wafer 300. The resultant output signals from the semiconductor wafer 300 under test are compared with the expected data generated by the semiconductor test system to determine whether the semiconductor wafer 300 performs properly.
FIG. 3 is a bottom view of the probe card 170 of FIG. 2. In this example, the probe card 170 has an epoxy ring on which a plurality of probe contactors 190 called needles or cantilevers are mounted. When the chuck 180 mounting the semiconductor wafer 300 moves upward in FIG. 2, the tips of the cantilevers 190 contact the pads or bumps on the wafer 300. The ends of the cantilevers 190 are connected to wires 194 which are further connected to transmission lines (not shown) formed in the probe card 170. The transmission lines are connected to a plurality of electrodes 197 which contact the pogo pins 141 of FIG. 2.
Typically, the probe card 170 is structured by a multilayer of polyimide substrates having ground planes, power planes, signal transmission lines on many layers. As is well known in the art, each of the signal transmission lines is designed to have a characteristic impedance such as 50 ohms by balancing the distributed parameters, i.e., dielectric constant of the polyimide, inductances, and capacitances of the signal within the probe card 170. Thus, the signal lines are impedance matched lines to achieve a high frequency transmission bandwidth to the wafer 300 providing current during steady state and high current peaks generated by the device's outputs switching. For removing noise, capacitors 193 and 195 are provided on the probe card between the power and ground planes.
An equivalent circuit of the probe card 170 is shown in FIG. 4 to explain the limitation of bandwidth in the conventional probe card technology. As shown in FIGS. 4A and 4B, the signal transmission line on the probe card 170 extends from the electrode 197, the strip (impedance matched) line 196, the wire 194 and the needle (cantilever) 190. Since the wire 194 and needle 190 are not impedance matched, these portions function as an inductor L in the high frequency band as shown in FIG. 4C. Because of the overall length of the wire 194 and needle 190 is around 20-30 mm, the significant frequency limitation is resulted in testing a high frequency performance of a device under test.
Other factors which limit the frequency bandwidth in the probe card 170 reside in the power and ground needles shown in FIGS. 4D and 4E. If the power line can provide large enough currents to the device under test, it will not seriously limit the operational bandwidth in testing the device. However, because the series connected wire 194 and needle 190 for supplying the power (FIG. 4D) as well as the series connected wire 194 and needle 190 for grounding the power and signals (FIG. 4E) are equivalent to inductors, the high speed current flow is seriously restricted.
Moreover, the capacitors 193 and 195 are provided between the power line and the ground line to secure a proper performance of the device under test by filtering out the noise or surge pulses on the power lines. The capacitors 193 have a relatively large value such as 10 .mu.F and can be disconnected from the power lines by switches if necessary. The capacitors 195 have a relatively small capacitance value such as 0.01 .mu.F and fixedly connected close to the DUT. These capacitors serve the function as high frequency decoupling on the power lines.
Accordingly, the most widely used probe contactors as noted above are limited to the frequency bandwidth of approximately 200 MHz which is insufficient to test recent semiconductor devices. It is considered, in the industry, that the frequency bandwidth be of at least that equal to the tester's capability which is currently on the order of 1 GHz or higher, will be necessary in the near future. Further, it is desired in the industry that a probe card is capable of handling a large number of semiconductor devices, especially memories, such as 32 or more, in parallel (parallel test) to increase test throughput.
To meet the next generation test requirements noted above, the inventors of this application has provided a new concept of contact structure in the U.S. application Ser. No. 09/099,614 "Probe Contactor Formed by Photolithography Process" filed Jun. 19, 1998. The contact structure is formed on a silicon or dielectric substrate through a photolithography process. FIGS. 5 and 6 show the contact structure in the above noted application. In FIG. 5, all of the contact structures 30 are formed on a silicon substrate 20 through the same photolithography process. When the semiconductor wafer 300 under test moves upward, the contact structures 30 contact corresponding contact targets (electrodes or pads) 320 on the wafer 300.
The contact structure 30 on the silicon substrate 20 can be directly mounted on a probe card such as shown in FIG. 3, or molded in a package, such as a traditional IC package having leads, so that the package is mounted on a probe card. However, packaging and interconnection of the contact structure 30 with respect to the probe card or equivalent thereof is not described in the patent application.